1. Field of the Invention
The present invention relates to a semiconductor packaging technique.
2. Description of the Related Art
A semiconductor package contains a semiconductor chip and presents external connections for interacting with the semiconductor chip. Semiconductor packages in their infancy used lead frames in connecting a semiconductor chip to an external system. The lead frames may include portions connected with the external system, for example outer leads, which may be arranged linearly, e.g., in a line or one-dimensionally, along the edges of a package. As the number of I/O pins and the operation speed of the semiconductor chips increased, however, semiconductor packages increasingly used printed circuit boards (PCBs) in place of the lead frames. The PCBs may have external connection terminals, for example solder balls, which may be arranged on a surface, e.g., two-dimensionally across the surface. The PCBs may meet the demand for the increased number of I/O pins and operation speed of a semiconductor chip.
Recently, board-on-chip (BOC) packages have been introduced. The BOC package may include a PCB provided on a chip having I/O pads. The BOC package may have a reduced electrical connection route between a chip and a substrate.
An adhesive may be used in attaching the PCB to the chip. The adhesive may include a film type and a liquid type. A liquid adhesive, having a predetermined viscosity, may be applied to the PCB using a screen-printing method.
FIG. 1 is a cross-sectional view of a conventional chip attachment process using an adhesive. Referring to FIG. 1, a semiconductor chip 10 may be placed on a stage 40. A head 50 may press down a PCB 20. The semiconductor chip 10 may be connected to the PCB 20, e.g., under a high temperature applied by the stage 40 and the head 50 and by a pressing force of the head 50 to cure the adhesive 30.
During a chip attachment process, faults may occur due to various causes. FIGS. 2A through 2E are cross-sectional views of some conventional faults caused by an abnormal flow of the adhesive 30.
For example, the faults related to the adhesive 30 may result from overflow of the adhesive 30 as shown in FIGS. 2A and 2B, or nonflow of the adhesive 30 as shown in FIGS. 2D and 2E.
Referring to FIG. 2A, the adhesive 30 may overflow 31 and run to the side surface of the PCB 20, thereby contaminating the lead patterns 21 of the PCB 20 or the head 50. Referring to FIG. 2B, the adhesive overflow 32 may invade the I/O pads 11 of the semiconductor chip 10, thereby contaminating the I/O pads 11. The contamination of the lead patterns 21 of the PCB 20 and/or the I/O pads 11 of the semiconductor chip 10 may unfavorably influence a subsequent wire bonding process. Referring to FIG. 2C, an adhesive residue 33 may unfavorably influence, e.g., cause distortion or misalignment during, a chip attachment process, thereby resulting in an excess attachment 34 and/or an incomplete attachment 35.
Referring to FIG. 2D, the adhesive 30 may flow incompletely and be cured in such condition to create a gap 36 between the semiconductor chip 10 and the PCB 20. During a subsequent encapsulation process, a filler 61 of a molding compound 60 may undesirably flow into the gap 36, thereby damaging a passivation layer 12 of the semiconductor chip 10. Referring to FIG. 2E, an incomplete flow of the adhesive 30 may cause a void 37 between the adhesive 30 and the PCB 20. The void 37 may induce swelling 38 of the PCB 20 during subsequent processes, e.g. such as during application of heat energy.
As described above, it is difficult to control the flow of the adhesive 30 during a chip attachment process. An abnormal flow of the adhesive 30 may result from a nonuniform application of the adhesive 30, an uneven pressing of the head 50 downward on the PCB 20, an excessive curing speed of the adhesive 30, and so on.